STIL Capture™ 
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STIL Capture is a highly automated tool flow which trivializes the process of producing a well-structured STIL ATE program from a functional verification scenario. STIL Capture allows engineers to record in-STIL from any mixed-language simulation and verification environment, greatly enhancing controllability, ease of use and communication between teams. 
STIL Capture Flow
STIL Capture removes the ad-hoc, error prone process of continuous translation of vectors between verification and ATE, allowing engineers to control STIL generation straight from simulation. Features include: - Capturing of event-based vector data in mixed-language simulation / verification
- On-the-fly test vector data cyclization
- Support for multiple waveform tables
- Precise, event-driven, run-time controllability for test-program generation
- Transaction annotation of STIL test programs
Unique Features
- –Easily control STIL generation to best support ATE needs and performance
Parameterization, runtime control and on-the-fly Wave generation are made easy, directly from the verification environment - Transaction Annotation
Produce structured STIL with functional verification information embedded in Pattern, PatternExec, PatternBurst, and other language constructs - Press-of-a-button delivery of DFT-based test cases
Combine STIL generation with DFT verification to drive DFT-based simulation scenarios directly to ATE and accelerate silicon debug applications
Benefits |
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