STIL Validate™ 
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–STIL Validate is a flexible tool capable of importing complete STIL-based ATE programs into advanced verification environments incorporating the latest verification language technologies such as IEEE 1647 ‘e‘ and IEEE 1800 SystemVerilog. Rather than creating separate, standalone test-benches for executing STIL in digital simulation, STIL Validate actually creates advanced verification objects that can communicate with the existing verification environment, enabling better visibility, enhanced reuse and better integration. STIL Simulate Flow Features include: - Parsing and validation of complete ATPG or other STIL test programs against IEEE standard specifications
- On-the-fly test vector data de-cyclization and event-driven simulation
- Support for Verilog, SystemVerilog and ‘e‘ testbenches and all major event-driven simulators
- Advanced STIL simulation integration such as transaction annotation, event triggering and assertions
- Integrated co-validation of STIL test programs and embedded test structures
Unique Features STIL Validate incorporates several unique capabilities: – - Accelerate simulation debug with Transaction Annotation and STIL Event Triggering
- Easily create integrated verification constructs such as assertions for STIL flows
- Co-verify STIL programs and Design-for-Test (DFT) in a single, unified, environment
STIL Validate with Transaction Annotation Benefits - Higher quality test engineering flows
Leverage built-in runtime STIL generation control features for more reliable generation at the source. Avoid excessive translation steps and intermediate data formats. - Enhances Design Productivity
STIL Validate features easy ATE Program Playback, leading to improved Test to Design transition and organization collaboration. - Accelerated silicon debug flows
STIL Validate accelerates the tedious task of logic-oriented silicon debug, allowing engineers to create high level associations between ATE programs and verification constructs such as assertions, checkers and coverage collectors. Engineers benefit from being able to trigger on STIL simulation events, trap and corner error conditions faster and easier.
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