Technical Paper Presentation: IEEE P1500 verification infrastructure at I-IP 2005

The paper introduces the concept of dynamic, constrained-random, automated verification of IEEE P1500-compliant test infrastructures. We expect such infrastructures to grow in size and applicability and DFT engineers try to address ever increasing complexity and heterogeneity in SoCs and NoCs. Applying a complete and disciplined verification methodology is becoming imperative for more and more technology companies.

Core-based design has quickly become today’s de-facto approach to building increasingly complex Systems-on-Chip (SoC). With the IEEE 1500 Proposal for a Standard for Embedded Core Test effectively addressing the important issues of reuse and interoperability with respect to testing core-based SoCs, as well as providing the infrastructure for building and operating testability features within cores from different suppliers, it has also become imperative to thoroughly verify the functionality of the complete test infrastructure within a certain SoC. In this paper we take a comprehensive approach to designing such a verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy. We also present a powerful implementation of such an environment using a contemporary Hardware Verification Language, along with experiences from application on several verification scenarios.