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Home > Solutions > Verification IP > e Verification Components > IEEE 1500 eVC > Features & Benefits


Q: What type of embedded cores does the IEEE 1500 eVC apply to?

A: The IEEE 1500 eVC applies to both wrapped and unwrapped IEEE 1500 compliant cores. The eVC supports out-of-the-box the full base functionality described in the IEEE standard, including mandatory instructions and registers.

Q: DFT insertion is mostly automated. Why do I need to verify my scan chains, BIST controllers, etc?

A: There are actually several reasons:

  1. Modern SoCs already include double-digit embedded cores, projected to reach as many as 40 by 2007. Whereas DFT logic such as scan chains used to only take up a small area in any given ASIC and was inserted as an ad-hoc element just before tapeout, it is now becoming part of a Unified Design Cycle (UDC).
  2. Most SoC integrate several embedded cores sourced from a third-party provider. Although this practice enables integrators to accelerate the product cycle and leverage experience not available in-house, it also poses several valid concerns as to the quality of the sourced core, including its DFT components and capabilities.
  3. Verification is a live process and applies at different abstraction layers and models. It is quite common, for example, that DFT elements that exist in certain embedded cores will stitched together by hand in the sub-system on system levels; testability infrastructures, just like the rest of the SoC design, need to be verified at different system configurations.

Q: The eVC seems to only support the serial TAM and mandatory instructions but my wrapper is connected to internal scan registers. Can I still use it?

A: The eVC supports the mandatory 1500 features, as described by the protocol. Such features are actually implemented as library based on the building blocks that the eVC provides; such building blocks can be used to describe arbitrary 1500 instructions, registers and even TAMs, depending on your design's needs.

Q: How about virtual registers?

A: Virtual registers are chains whose cells can also be part of other chains. For example, a designer could define a register that connects part of the WBR to an internal scan path and which is selectable by a separate instruction. The eVC can support such register definitions, providing generation, monitoring and functional coverage collections, as well as maintaining cell state when switching to other instructions.

Q: My system-level interface is a JTAG tap. How can I use the eVC to verify at that level?

A: The eVC has a dual built-in BFM which allows the user to drive sequences in either P1500 native or 1149.1 (JTAG) mode. This feature gracefully allows testbench migration from a core-level to a system-level environment where a JTAG decoder is used to translate JTAG TAP signalling to a 1500 TAM.

Q: How about acceleration?

A: Since the eVC requires no feedback between the DUT and sequence driver/BFM, its performance could be greatly enhanced on a simulaiton accelaration plarform. We are currently evaluating performance on Verisity's SpeXtreme platform. Please contact us for details.

Q: I'm interested in seeing the eVC at work. How can I setup a demo/evaluation?

A: Please contact us! We'll be happy to set you up with an evaluation of the eVC with no strings attached.