This article describes the test wrapper implementation of a popular embedded microprocessor, along with an automated approach for verifying the wrapper's compliance to the standard.

Earlier this year, Globetech Solutions announced STIL Verifier, the industry’s fastest route from functional verification to functional silicon test and debug. STIL Verifier aims at extending verification capabilities into the post-silicon validation domain. Its goal is also to leverage verification environment constructs, process data, and design knowledge to increase effectiveness and reduce cost during debug, validation, and volume test of semiconductor devices.

In this article, publised in the Cadence Incisive Newsletter, we discuss the clear advantages Scenario Builder offers to the VIP ecosystem, as well as how VIP providers can leverage Scenario Builder to extend benefits to the end user.

Project management and automation are quickly becoming the most critical elements in the overall design and verification process. The most effective verification management strategy requires that design teams focus on some key features for success.

This paper introduces a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.

This brief article discusses how to plan DFT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical, and fully automated path from specification to closure.