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Papers by Globetech Solutions and Partners

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Incisive Enterprise Scenario Builder Inceases Value and Verification IP Reuse [Download - application/pdf]
In this article, publised in the Cadence Incisive Newsletter, we discuss the clear advantages Scenario Builder offers to the VIP ecosystem, as well as how VIP providers can leverage Scenario Builder to extend benefits to the end user.
Systematically Implementing Late Engineering Changes on Your Project: Do's and Don'ts [Download - application/pdf]
Partner Pick
Project management and automation are quickly becoming the most critical elements in the overall design and verification process. The most effective verification management strategy requires that design teams focus on some key features for success.
Designing a CE-ATA Verification Environment for SoC Applications [Download - application/pdf]

In this paper we describe a verification environment developed for the emerging CE-ATA interface that can be used as a plug-n-play verification component into any SoC that implements a CE-ATA bus. The paper was presented at IP/SoC 2005, Grenoble, France.

A Unified DFT Verification Methodology [Download - application/pdf]
This paper introduces a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.
How are you planning to verify all that DfT? [Download - application/pdf]
This brief article discusses how to plan DFT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical, and fully automated path from specification to closure.
Good and Bad Verification Planning [Download - application/pdf]
Partner Pick
Project management is all about planning and execution. But if everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes down to the adage, “Begin with the end in mind.” A good plan contains detailed goals using measurable metrics, along with optimal resource usage and realistic schedule estimates.
Towards and IEEE P1500 Verification Infrastructure: A Comprehensive Approach [Download - application/pdf]
Presented at the 3rd IEEE Workshop on Infrastructure IP, Palm Spings, California, USA, this paper discusses a comprehensive approach to designing a DFT verification infrastructure based on a dynamic, constrained-random, coverage-driven verification methodology, which can be part of the overall chip-level validation strategy.

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